1. Field of the Invention
This invention relates to semiconductor devices, and in particular to a semiconductor device having a hybrid trench isolation structure that combines a full trench isolation structure and a partial trench isolation structure.
2. Description of the Background Art
A semiconductor device of SOI (Silicon On Insulator) structure (hereafter called “SOI device”), which is formed on an SOI substrate including a buried oxide film and an SOI layer provided on a silicon substrate, allows parasitic capacitance reduction and operates with stability at high speed with low power consumption, and is used for a portable device and the like.
By way of example, an SOI device has a full trench isolation (FTI) structure in which elements are electrically isolated by a full trench isolation insulating film formed by providing a trench that reaches the buried oxide film in the surface of the SOI layer, and filling the trench with an insulating material.
However, there have been various kinds of problems resulting from a substrate floating effect, such as the accumulation of carriers (holes in an NMOS) generated by an impact ionization phenomenon in a channel forming region which leads to kinks, deterioration of operating breakdown voltage, and the occurrence of frequency dependency of delay time due to potential instability of the channel forming region.
Thus devised is a partial trench isolation (PTI) structure which is formed by providing a trench in the surface of the SOI layer while leaving the SOI layer in a predetermined thickness between the bottom of the trench and the buried oxide film, and filling the trench with an insulating material.
The PTI structure allows movements of carriers through a well region under the trench isolation insulating film thus preventing the accumulation of carriers in a channel forming region, and also allows the potential of the channel forming region to be fixed through the well region, not causing the various problems resulting from the substrate floating effect.
In addition, there has been proposed a hybrid trench isolation (HTI) structure that combines the respective characteristics of the FTI structure and the PTI structure, as described in Japanese Patent Application Laid-Open Nos. 2001-230315 (FIG. 1) and 2000-243973 (FIGS. 55 to 57).
The HTI structure has a cross-sectional shape that includes a full trench portion reaching the buried oxide film through the SOI layer, and a partial trench portion having the SOI layer provided thereunder.
With smaller semiconductor elements, the likelihood is that a gate length of a transistor, spacing between wirings, and the like will be shortened, and dimensions in the vertical direction (direction perpendicular to a substrate main surface) such as a gate height, the thickness of an interlayer insulating film, the thickness of an SOI layer, and the like will be correspondingly reduced as well, resulting in a scale-down of the whole device.
With the progress of scale-down, however, it becomes necessary to reduce the thickness of the isolation oxide film in the PTI structure as well. When a gate electrode extends over the isolation oxide film, the parasitic capacitance of the gate electrode may increase too much to ignore.